ARM Cortex-M3 User Manual

Nested Vectored Interrupt Controller
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-29
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Figure 8-14 System Handler Priority Registers bit assignments
Table 8-20 describes the bit assignments of the System Handler Priority Registers.
System Handler Control and State Register
Use the System Handler Control and State Register to:
• enable or disable the system handlers
• determine the pending status of bus fault, mem manage fault, and SVC
• determine the active status of the system handlers.
If a fault condition occurs while its fault handler is disabled, the fault escalates to a Hard
Fault.
The register address, access type, and Reset state are:
Address
0xE000ED24
Access Read/write
Reset state
0x00000000
Figure 8-15 on page 8-30 shows the bit assignments of the System Handler and State
Control Register.
31 23 16 15 7 0
PRI_5 PRI_4PRI_6
24 8
PRI_7
PRI_9 PRI_8PRI_10PRI_11
PRI_12PRI_13PRI_14PRI_15
E000ED18
E000ED1C
E000ED20
Table 8-20 System Handler Priority Registers bit assignments
Bits Field Function
[31:24] PRI_N3 Priority of system handler 7, 11, and 15. Reserved, SVCall, and SysTick.
[23:16] PRI_N2 Priority of system handler 6, 10, and 14. Usage Fault, reserved, and PendSV.
[15:8] PRI_N1 Priority of system handler 5, 9, and 13, Bus Fault, reserved, and reserved.
[7:0] PRI_N Priority of system handler 4, 8, and 12. Mem Manage, reserved, and Debug Monitor.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit