ARM Cortex-M3 User Manual

Embedded Trace Macrocell Interface
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 15-3
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15.2 CPU ETM interface port descriptions
The processor has a port that enables the ETM to determine the instruction execution
sequence. These port descriptions are described in Table 15-1.
Table 15-1 ETM interface ports
Port name Direction Qualified by Description
ETMIVALID Output No qualifier Instruction in execute is valid. Marks that an opcode has
entered the first cycle of execute.
ETMIBRANCH Output ETMIVALID Opcode is a branch target. Marks that current code is the
destination of a Program Counter (PC) modifying event
(branch, interrupt processing).
ETMIINDBR Output ETMIBRANCH Opcode branch target is indirect. Marks that the current
opcode is a branch target whose destination the PC
contents cannot deduce. For example, LSU, register
move, or interrupt processing.
ETMDVALID Output No qualifier Signals that the current data address as seen by the Data
Watchpoint and Trace (DWT) is valid on this cycle.
ETMICCFAIL Output ETMIVALID Opcode condition code fail or pass. Marks if the current
opcode has failed or passed its conditional execution
check. An opcode is conditionally executed if it is a
conditional branch, or for all other opcode found in an IT
block.
ETMINTSTAT[2:0] Output No qualifier Interrupt status. Marks the interrupt status of the current
cycle:
000 no status
001 interrupt entry
010 interrupt exit
011 interrupt return
100 - Vector fetch and stack push. ETMINTSTAT
Entry/Return is asserted in the first cycle of the new
interrupt context. Exit occurs without ETMIVALID.
ETMINTNUM[8:0] Output ETMINTSTAT Interrupt number. Marks the interrupt number of the
current execution context.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit