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General| Architecture | ARMv7-M |
|---|---|
| Instruction Set | Thumb-2 |
| Pipeline Stages | 3-stage |
| Interrupts | Nested Vectored Interrupt Controller (NVIC) |
| Interrupt Controller | Nested Vectored Interrupt Controller (NVIC) |
| Memory Protection Unit | Optional |
| Power Consumption | Varies by implementation |
| Max Clock Speed | Up to 100 MHz |
| Debugging | JTAG and Serial Wire Debug (SWD) |
| Operating Voltage | 1.8V to 3.6V |
| Manufacturing Process | Varies by implementation |
| Core Type | 32-bit |
Describes the Cortex-M3 processor's low-power features, ARMv7-M architecture, and core components.
Details the processor's components, hierarchy, and implementation options, including core, NVIC, bus matrix, etc.
Summarizes functional differences between processor releases like r0p0, r1p0, r1p1, and r2p0.
Explains the ARMv7-M architecture implementation, including Thumb instructions and operating states.
Details the processor's 32-bit registers, including general-purpose, stack pointers, PC, and xPSR.
Describes how the processor views memory and its support for little-endian and big-endian data formats.
Lists and describes registers controlling processor functionality, including NVIC, Core Debug, and System Debug.
Provides a summary of registers for core debug operations via AHB-AP or internal PPB.
Lists registers for Flash Patch and Breakpoint (FPB) and Data Watchpoint and Trace (DWT) units.
Shows the processor's fixed memory map, including vendor-specific regions, external RAM, and peripheral spaces.
Explains the bit-band regions in SRAM and Peripheral memory, and the mapping formula for accessing bits.
Describes how the processor and NVIC prioritize and handle exceptions, including state saving and tail-chaining.
Details various exception types like Reset, NMI, Hard Fault, Memory Management, Bus Fault, and Usage Fault.
Explains processor support for two stacks (main/process) and privilege levels for Thread and Handler modes.
Describes the three functional clock inputs: FCLK, HCLK, and DAPCLK, and their domains.
Lists the processor reset inputs: PORESETn, SYSRESETn, SYSRESETREQ, and DAPRESETn.
Shows reset signals, combinations, and applications for power-on, system, and SWJ-DP reset modes.
Explains processor use of gated clocks and system sleep modes for power reduction.
Details supported sleep modes (Sleep-now, Sleep-on-exit, Deep-sleep) controlled by the System Control Register.
Describes how the SLEEPING signal gates the HCLK clock for processor power reduction.
Explains NVIC's role in low-latency exception handling, power management, and System Control Registers.
Lists NVIC registers and their addresses within the System Control Space.
Details enabling interrupts and determining currently enabled ones via Set-Enable Registers.
Describes MPU for memory protection, supporting regions, permissions, and attributes.
Summarizes and describes MPU registers, including Type, Control, and Region registers.
Explains access permission bits (TEX, C, B, AP, XN) controlling access to memory regions.
Explains core debug access via debug registers through AHB-AP or internal PPB.
Lists registers for debug operations, including Debug Halting Control and Status Register.
Details halting the core using C_DEBUGEN and C_HALT bits in the Debug Halting Control and Status Register.
Introduces system debug components like FPB, DWT, ITM, and ETM for debug, trace, and profiling.
Explains debug access via AHB-AP, driven by SW-DP or SWJ-DP components.
Describes the Flash Patch and Breakpoint (FPB) unit for implementing hardware breakpoints and code patches.
Details the processor's four bus interfaces: ICode, DCode, System, and External Private Peripheral Bus (PPB).
Explains the ICode interface, a 32-bit AHB-Lite bus for instruction fetches and vector fetches.
Describes the DCode interface, a 32-bit AHB-Lite bus for data and debug accesses to Code memory space.
Explains the Debug Port (DP) as an AHB-AP interface for debug accesses, supporting SWJ-DP or SW-DP.
Introduces the Embedded Trace Macrocell (ETM) as an optional component for program execution reconstruction.
Lists ETM resources on Cortex-M3, including architecture version, comparators, and FIFO size.
Details the ETM programmer's model, APB interface, and registers like ETM Control and Configuration Code.
Explains the ETM interface for connecting an ETM to the processor for instruction trace.
Describes ETM interface ports like ETMIVALID, ETMIBRANCH, and ETMINTSTAT for execution sequence.
Describes the AHB trace macrocell (HTM) interface for connecting an AHB trace macrocell for data trace.
Introduces the Trace Port Interface Unit (TPIU) as a bridge for trace data from ETM/ITM to a Trace Port Analyzer.
Summarizes TPIU registers including Sync Port Sizes, Async Clock Prescaler, and Formatter registers.
Describes the Formatter and Flush Status Register for reading the status of the TPIU formatter.
Explains the role of system architecture in instruction timing and factors influencing it.
Provides cycle information for Thumb subset instructions, including data operations, branches, and load-stores.
Details input and output port timing parameters as percentages of the processor clock cycle.
Lists timing parameters for miscellaneous, low power, interrupt, AHB, PPB, debug, and ETM ports.
Lists and describes the clock signals: HCLK, FCLK, and DAPCLK.
Lists and describes the reset signals: PORESETn, SYSRESETn, SYSRESETREQ, and DAPRESETn.
Describes miscellaneous signals like LOCKUP, CURRPRI, HALTED, DBGRESTARTED, TXEV, TRCENA, INTERNALSTATE, BIGEND, EDBGRQ.
Lists technical changes between issue E and issue F of the manual.
Defines abort as a mechanism indicating an invalid memory access or invalid data return.
Describes AHB as a bus protocol with a fixed pipeline for address/control and data phases.
