ARM Cortex-M3 User Manual

Memory Map
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4.2 Bit-banding
The processor memory map includes two bit-band regions. These occupy the lowest
1MB of the SRAM and Peripheral memory regions respectively. These bit-band regions
map each word in an alias region of memory to a bit in a bit-band region of memory.
The memory map has two 32-MB alias regions that map to two 1-MB bit-band regions:
• Accesses to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band
region.
• Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral
bit-band region.
A mapping formula shows how to reference each word in the alias region to a
corresponding bit, or target bit, in the bit-band region. The mapping formula is:
bit_word_offset = (byte_offset x 32) + (bit_number × 4)
bit_word_addr = bit_band_base + bit_word_offset
where:
•
Bit_word_offset is the position of the target bit in the bit-band memory region.
•
Bit_word_addr is the address of the word in the alias memory region that maps to
the targeted bit.
•
Bit_band_base is the starting address of the alias region.
•
Byte_offset is the number of the byte in the bit-band region that contains the
targeted bit.
•
Bit_number is the bit position (0-7) of the targeted bit.
Figure 4-2 on page 4-6 shows examples of bit-band mapping between the SRAM
bit-band alias region and the SRAM bit-band region:
• The alias word at
0x23FFFFE0 maps to bit [0] of the bit-band byte at 0x200FFFFF :
0x23FFFFE0 = 0x22000000 + ( 0xFFFFF*32 ) + 0*4.
• The alias word at
0x23FFFFFC maps to bit [7] of the bit-band byte at 0x200FFFFF :
0x23FFFFFC = 0x22000000 + ( 0xFFFFF*32 ) + 7*4.
• The alias word at
0x22000000 maps to bit [0] of the bit-band byte at 0x20000000 :
0x22000000 = 0x22000000 + (0*32) + 0 *4.
• The alias word at
0x2200001C maps to bit [7] of the bit-band byte at 0x20000000 :
0x2200001C = 0x22000000 + ( 0*32 ) + 7*4.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit