ARM Cortex-M3 User Manual

Signal Descriptions
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A.8 System bus interface
Table A-8 lists the signals of the system bus interface.
Table A-8 System bus interface
Name Direction Description
HADDRS[31:0] Output 32-bit address.
HTRANSS[1:0] Output Indicates the type of the current transfer. Can be IDLE, NONSEQUENTIAL, OR
SEQUENTIAL.
HSIZES[2:0] Output Indicates the size of the access. Can be 8, 16, or 32 bits.
HBURSTS[2:0] Output Indicates if the transfer is part of a burst.
HPROTS[3:0] Output Provides information on the access.
HWDATAS[31:0] Output 32-bit write data bus.
HWRITES Output Write not read.
HMASTLOCKS Output Indicates a transaction that must be atomic on the bus. This is only for bit-band
writes (performed as read-modify-write).
EXREQS Output Exclusive request.
MEMATTRS[1:0] Output Memory attributes. Bit 0 = Allocate, Bit 1 = shareable.
HMASTERS[1:0] Output Indicates the current system bus master:
• 0 = Core data side accesses or DAP access with MasterType set to 0.
• 1 = DAP accesses with MasterType set to 1.
• 2 = Core instruction side accesses. These include vector fetches that are
marked as data by HPROTS[0].
• 3 = Reserved. This value cannot appear on HMASTERS.
HRDATAS[31:0] Input Read data bus.
HREADYS Input When HIGH indicates that a transfer has completed on the bus. The signal is driven
LOW to extend a transfer.
HRESPS[1:0] Input The transfer response status. OKAY or ERROR.
EXRESPS Input Exclusive response.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit