ARM Cortex-M3 User Manual

System Debug
11-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
Table 11-6 DWT register summary
Name Type Address Reset value Description
DWT_CTRL Read/write
0xE0001000 0x40000000 See DWT Control Register on page 11-15
DWT_CYCCNT Read/write
0xE0001004
0x00000000
See DWT Current PC Sampler Cycle Count
Register on page 11-19
DWT_CPICNT Read/write
0xE0001008 -See DWT CPI Count Register on page 11-20
DWT_EXCCNT Read/write
0xE000100C - See DWT Exception Overhead Count Register on
page 11-20
DWT_SLEEPCNT Read/write
0xE0001010 - See DWT Sleep Count Register on page 11-21
DWT_LSUCNT Read/write
0xE0001014 - See DWT LSU Count Register on page 11-22
DWT_FOLDCNT Read/write
0xE0001018 - See DWT Fold Count Register on page 11-23
DWT_PCSR Read-only
0xE000101C -See DWT Program Counter Sample Register on
page 11-24
DWT_COMP0 Read/write
0xE0001020 -See DWT Comparator Registers on page 11-24
DWT_MASK0 Read/write
0xE0001024 -See DWT Mask Registers 0-3 on page 11-25
DWT_FUNCTION0 Read/write
0xE0001028 0x00000000 See DWT Function Registers 0-3 on page 11-25
DWT_COMP1 Read/write
0xE0001030 -See DWT Comparator Registers on page 11-24
DWT_MASK1 Read/write
0xE0001034 -See DWT Mask Registers 0-3 on page 11-25
DWT_FUNCTION1 Read/write
0xE0001038 0x00000000 See DWT Function Registers 0-3 on page 11-25
DWT_COMP2 Read/write
0xE0001040 -See DWT Comparator Registers on page 11-24
DWT_MASK2 Read/write
0xE0001044 -See DWT Mask Registers 0-3 on page 11-25
DWT_FUNCTION2 Read/write
0xE0001048 0x00000000 See DWT Function Registers 0-3 on page 11-25
DWT_COMP3 Read/write
0xE0001050 -See DWT Comparator Registers on page 11-24
DWT_MASK3 Read/write
0xE0001054 -See DWT Mask Registers 0-3 on page 11-25
DWT_FUNCTION3 Read/write
0xE0001058 0x00000000 See DWT Function Registers 0-3 on page 11-25
PID4 Read-only
0xE0001FD0 0x04 Val ue 0x04
PID5 Read-only 0xE0001FD4 0x00 Val ue 0x00

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit