ARM Cortex-M3 User Manual

System Debug
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ITM Trace Control Register
Use this register to configure and control ITM transfers.
Note
You can only write to this register in privilege mode.
The register address, access type, and Reset state are:
Access Read/write
Address
0xE0000E80
Reset 0x00000000
Figure 11-14 shows the ITM Control Register bit assignments.
Figure 11-14 ITM Trace Control Register bit assignments
Table 11-22 describes the bit assignments of the ITM Control Register.
31
43 0
12
7
9810
15
16
Reserved
SYNCENA
TSENA
ITMENA
TSPrescale
DWTENA
24
23
Reserved
ATBID
5
SWOENA
BUSY
22
Reserved
Table 11-22 ITM Trace Control Register bit assignments
Bits Field Function
[31:24] - 0b00000000.
[23] BUSY Set when ITM events present and being drained
[22:16] ATBID ATB ID for CoreSight system.
[15:10] - 0b000000.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit