ARM Cortex-M3 User Manual

AC Characteristics
19-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
Table 19-12 shows the timing parameters for the PPB output ports.
Table 19-13 shows the timing parameters for the debug interface output ports.
Table 19-12 PPB output ports timing parameters
Output delay Min. Output delay Max. Signal name
Clock uncertainty 50% PADDR31
Clock uncertainty 50% PADDR[19:2]
Clock uncertainty 50% PSEL
Clock uncertainty 50% PENABLE
Clock uncertainty 50% PWRITE
Clock uncertainty 50% PWDATA[31:0]
Table 19-13 Debug interface output ports timing parameters
Output delay Min. Output delay Max. Signal name
Clock uncertainty 50% SWV
Clock uncertainty 50% TRACECLK
Clock uncertainty 50% TRACEDATA[3:0]
Clock uncertainty 50% TDO
Clock uncertainty 50% SWDO
Clock uncertainty 50% nTDOEN
Clock uncertainty 50% SWDOEN
Clock uncertainty 50% DAPREADY
Clock uncertainty 50% DAPSLVERR
Clock uncertainty 50% DAPRDATA[31:0]
Clock uncertainty 50% ATVAL ID
Clock uncertainty 50% AFREADY
Clock uncertainty 50% ATDATA[7 :0]
Clock uncertainty 50% DBGRESTARTED

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit