ARM Cortex-M3 User Manual

System Debug
11-36 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Table 11-23 describes the bit assignments of the ITM Integration Write Register.
Note
Bit [0] drives ATVALIDM when mode is set.
ITM Integration Read Register
Use this register to read the value on ATREADYM
Figure 11-16 shows the ITM Integration Read Register bit assignments.
Figure 11-16 ITM Integration Read Register bit assignments
Table 11-24 describes the bit assignments of the ITM Integration Read Register.
ITM Integration Mode Control Register
Use this register to enable write accesses to the Control Register.
Table 11-23 ITM Integration Write Register bit assignments
Bits Field Function
[31:1] - Reserved
[0] ATVALIDM When the integration mode is set:
0 = ATVALIDM clear
1 = ATVALIDM set.
31
0
1
Reserved
ATREADYM
Table 11-24 ITM Integration Read Register bit assignments
Bits Field Function
[31:1] - Reserved
[0] ATREADYM Value on ATREADYM

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit