ARM Cortex-M3 User Manual

Nested Vectored Interrupt Controller
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-7
Unrestricted Access Non-Confidential
8.2.2 NVIC register descriptions
The sections that follow describe how to use the NVIC registers.
Note
The Memory Protection Unit (MPU) registers, and the debug registers are described in
Chapter 9 Memory Protection Unit and Chapter 10 Core Debug respectively.
Interrupt Controller Type Register
Read the Interrupt Controller Type Register to see the number of interrupt lines that the
NVIC supports.
The register address, access type, and Reset state are:
Address
0xE000E004
Access Read-only
Reset state Depends on the number of interrupts defined in this processor
implementation.
Figure 8-1 shows the bit assignments of the Interrupt Controller Type Register.
Figure 8-1 Interrupt Controller Type Register bit assignments
31 54 0
INTLINESNUM Reserved

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit