ARM Cortex-M3 User Manual

System Debug
11-26 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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• Emit data or PC couples, trigger the ETM, or generate a watchpoint depending on
the operation defined by FUNCTION.
The register address, access type, and Reset state are:
Address
0xE0001028, 0xE0001038 , 0xE0001048 , 0xE0001058
Access Read/write
Address 0x00000000
Figure 11-12 shows the bit assignments of DWT Function Registers 0-3.
Figure 11-12 DWT Function Registers 0-3 bit assignments
Table 11-17 describes the bit assignments of DWT Function Registers 0-3.
31 1 06 5 4 3 2
Reserved
CYCMATCH
EMITRANGE
FUNCTION
7825 24 23 1920 16 15 12 11 10 9
MATCHED
Reserved
DATAVADDR1
DATAVADDR0
DATAVSIZE
DATAVMATCH
LNK1ENA
Reserved
Reserved
Table 11-17 Bit functions of DWT Function Registers 0-3
Bits Field Function
[31:25] - Reserved.
[24] MATCHED This bit is set when the comparator matches, and indicates that the operation defined by
FUNCTION has occurred since this bit was last read. This bit is cleared on read.
[23:20] - Reserved.
[19:16] DATAVADDR1 Identity of a second linked address comparator for data value matching when
DATAVMATCH == 1 and LNK1ENA == 1.
[15:12] DATAVADDR0 Identity of a linked address comparator for data value matching when DATAVMATCH ==
1.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit