Memory Protection Unit
9-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
Reset state
0x00000800
Figure 9-1 shows the bit assignments of the MPU Type Register.
Figure 9-1 MPU Type Register bit assignments
Table 9-2 describes the bit assignments of the MPU Type Register.
MPU Control Register
Use the MPU Control Register to:
• enable the MPU
• enable the default memory map (background region)
• enable the MPU when in Hard Fault, Non-maskable Interrupt (NMI), and
FAULTMASK escalated handlers.
When the MPU is enabled, at least one region of the memory map must be enabled for
the MPU to function unless the PRIVDEFENA bit is set. If the PRIVDEFENA bit is set
and no regions are enabled, then only privileged code can operate.
When the MPU is disabled, the default address map is used, as if no MPU is present.
When the MPU is enabled, only the system partition and vector table loads are always
accessible. Other areas are accessible based on regions and whether PRIVDEFENA is
enabled.
Reserved
31 24 23 16 15 8 7 1 0
IREGION DREGION Reserved
SEPARATE
Table 9-2 MPU Type Register bit assignments
Bits Field Function
[31:24] - Reserved.
[23:16] IREGION Because the processor core uses only a unified MPU, IREGION always contains
0x00
.
[15:8] DREGION Number of supported MPU regions field. DREGION contains
0x08
if the implementation
contains an MPU indicating eight MPU regions, otherwise it contains
0x00
.
[7:0] - Reserved.
[0] SEPARATE Because the processor core uses only a unified MPU, SEPARATE is always 0.
To Next Page
Loading...
Need help?
General
