ARM Cortex-M3 User Manual

System Control
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 3-9
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Instrumentation Trace Macrocell registers
Table 3-5 gives a summary of the Instrumentation Trace Macrocell (ITM) registers. For
a detailed description of the ITM registers, see Chapter 11 System Debug
Table 3-5 ITM register summary
Name Type Address Reset value
Stimulus Ports 0-31 Read/write
0xE0000000 - 0xE000007C -
Trace Enable Read/write
0xE0000E00 0x00000000
Trace Privilege Read/write 0xE0000E40 0x00000000
Trace Control Register Read/write 0xE0000E80 0x00000000
Integration Write Write-only 0xE0000EF8 0x00000000
Integration Read Read-only 0xE0000EFC 0x00000000
Integration Mode Control Read/write 0xE0000F00 0x00000000
Lock Access Register Write-only 0xE0000FB0 0x00000000
Lock Status Register Read-only 0xE0000FB4 0x00000003
PID4 Read-only 0xE0000FD0 0x00000004
PID5 Read-only 0xE0000FD4 0x00000000
PID6 Read-only 0xE0000FD8 0x00000000
PID7 Read-only 0xE0000FDC 0x00000000
PID0 Read-only 0xE0000FE0 0x00000001
PID1 Read-only 0xE0000FE4 0x000000B0
PID2 Read-only 0xE0000FE8 0x0000002B
PID3 Read-only 0xE0000FEC 0x00000000
CID0 Read-only 0xE0000FF0 0x0000000D
CID1 Read-only 0xE0000FF4 0x000000E0
CID2 Read-only 0xE0000FF8 0x00000005
CID3 Read-only 0xE0000FFC 0x000000B1

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit