ARM Cortex-M3 User Manual

Memory Protection Unit
9-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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9.1 About the MPU
The MPU is an optional component for memory protection. The processor supports the
standard ARMv7 Protected Memory System Architecture (PMSAv7) model. The MPU
provides full support for:
• protection regions
• overlapping protection regions, with ascending region priority:
— 7 = highest priority
— 0 = lowest priority.
• access permissions
• exporting memory attributes to the system.
MPU mismatches and permission violations invoke the programmable-priority
MemManage fault handler. For more information, see Memory Manage Fault Address
Register on page 8-40.
You can use the MPU to:
• enforce privilege rules
• separate processes
• enforce access rules.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit