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Chapter 9

Memory Protection Unit

This chapter describes the processor Memory Protection Unit (MPU). It contains the

following sections:

• About the MPU on page 9-2

• MPU programmer’s model on page 9-3

• Interrupts and updating the MPU on page 9-19

• MPU access permissions on page 9-13

• MPU aborts on page 9-15

• Updating an MPU region on page 9-16.

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ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit