ARM Cortex-M3 User Manual

Nested Vectored Interrupt Controller
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-25
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Note
SYSRESETREQ is cleared by a system reset, which means that asserting
VECTRESET at the same time might cause SYSRESETREQ to be cleared in the
same cycle as it is written to. This might prevent the external system from seeing
SYSRESETREQ. It is therefore recommended that VECTRESET and
SYSRESETREQ be used exclusively and never both written to 1 at the same time.
System Control Register
Use the System Control Register for power-management functions:
• signal to the system when the processor can enter a low power state
• control how the processor enters and exits low power states.
The register address, access type, and Reset state are:
Address
0xE000ED10
Access Read/write
Reset state
0x00000000
Figure 8-12 shows the bit assignments of the System Control Register.
Figure 8-12 System Control Register bit assignments
31 4 3 2 1 0
Reserved
Reserved
SLEEPDEEP
SLEEPONEXIT
Reserved
5
SEVONPEND

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit