Signal Descriptions
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. A-9
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A.7 DCode interface
Table A-7 lists the signals of the DCode interface.
Table A-7 DCode interface
Name Direction Description
HADDRD[31:0] Output 32-bit data address bus
HTRANSD[1:0] Output Indicates whether the current transfer is IDLE, NONSEQUENTIAL, or
SEQUENTIAL.
HWRITED Output Write not read
HSIZED[2:0] Output Indicates the size of the access. Can be 8, 16, or 32 bits.
HBURSTD[2:0] Output Indicates if the transfer is part of a burst. Data accesses are performed as INCR on
Cortex-M3.
HPROTD[3:0] Output Provides information on the access. Always indicates cacheable and non-bufferable
on this bus.
EXREQD Output Exclusive request.
MEMATTRD[1:0] Output Memory attributes.
Always 01 for this bus (non-shareable, allocate).
HMASTERD[1:0] Output Indicates the current DCode bus master:
• 0 = Core data side accesses.
• 1 = DAP accesses.
• 2 = Core instruction side accesses. These include vector fetches that are
marked as data by HPROTD[0]. This value cannot appear on HMASTERD.
• 3 = Reserved. This value cannot appear on HMASTERD.
HWDATAD[31:0] Output 32-bit write data bus.
HREADYD Input When HIGH indicates that a transfer has completed on the bus. This signal is driven
LOW to extend a transfer.
HRESPD[1:0] Input The transfer response status. OKAY or ERROR.
HRDATAD[31:0] Input Read data.
EXRESPD Input Exclusive response.
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