ARM Cortex-M3 User Manual

Bus Interface
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12.7 External private peripheral interface
The external private peripheral interface is an APB (AMBA v3.0) bus. Data and debug
accesses to the External Peripheral memory space (
0xE0040000 - 0xE00FFFFF ) are
performed over this bus. The TPIU and any vendor specific components populate this
bus. Core data accesses have higher priority than debug accesses, so debug accesses are
waited until core accesses have completed when there are simultaneous core and debug
access to this bus. Only the address bits necessary to decode the External PPB space are
supported on this interface. These address bits are bits [19:2] of PADDR.
PADDR31 is driven as a sideband signal on this bus. When the signal is HIGH, it
indicates that the AHB-AP debug is the requesting master. When the signal is LOW, it
indicates that the core is the requesting master.
Unaligned accesses to this bus are architecturally Unpredictable and are not supported.
The processor drives out the original HADDR[1:0] request from the core and does not
convert the request into multiple aligned accesses.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit