ARM Cortex-M3 User Manual

AC Characteristics
19-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Table 19-5 shows the timing parameter for the Private Peripheral Bus (PPB) port.
Table 19-6 shows the timing parameters for the debug input ports.
Table 19-5 PPB input port timing parameters
Input delay Min. Input delay Max. Signal name
Clock uncertainty 50% PRDATA[31:0]
Clock uncertainty 50% PREADY
Clock uncertainty 50% PSLVERR
Table 19-6 Debug input ports timing parameters
Input delay Min. Input delay Max. Signal name
Clock uncertainty 10% nTRST
Clock uncertainty 50% SWDITMS
Clock uncertainty 50% TDI
Clock uncertainty 50% DAPRESETn
Clock uncertainty 50% DAPSEL
Clock uncertainty 50% DAPEN
Clock uncertainty 50% DAPENABLE
Clock uncertainty 50% DAPCLKEN
Clock uncertainty 50% DAPWRITE
Clock uncertainty 50% DAPABORT
Clock uncertainty 50% DAPADDR[31:0]
Clock uncertainty 50% DAPWDATA[31:0]
Clock uncertainty 50% ATREADY
Clock uncertainty 50% DBGRESTART
Clock uncertainty 50% FIXHMASTERTYPE

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit