ARM Cortex-M3 User Manual

Exceptions
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-33
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Table 5-15 shows exception subtype transitions.
Table 5-15 Exception subtype transitions
Intended
activation
subtype Triggering event Activation Priority effect
Thread Reset signal Asynchronous Immediate, thread is lowest
ISR/NMI HW signal or set-pend Asynchronous Pre-empt or tail-chain according to priority
Monitor
Debug event
a
Synchronous If priority less than or equal to current, hard fault
SVCall SVC instruction Synchronous If priority less than or equal to current, hard fault
PendSV Software pend request Chain Pre-empt or tail-chain according to priority
UsageFault Undefined instruction Synchronous If priority greater than or equal to current, hard fault
NoCpFault Access to absent CP Synchronous If priority greater than or equal to current, hard fault
BusFault Memory access error Synchronous If priority greater than or equal to current, hard fault
MemManage MPU mismatch Synchronous If priority greater than or equal to current, hard fault
HardFault Escalation Synchronous Higher than all except NMI
FaultEscalate Escalate request from
Configurable fault
handler
Chain Boosts priority of local handler to same as hard fault so it can
return and chain to Configurable Fault handler
a. While halting not enabled.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit