ARM Cortex-M3 User Manual

Programmer’s Model
2-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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2.1 About the programmer’s model
The processor implements the ARMv7-M architecture. This includes all the 16-bit
Thumb instructions and the base 32-bit Thumb instructions. The processor cannot
execute ARM instructions. For more information about the ARMv7-M Thumb
instruction set see the ARMv7-M Architecture Reference Manual.
2.1.1 Operating modes
The processor supports two modes of operation, Thread mode and Handler mode:
• Thread mode is entered on Reset, and can be entered as a result of an exception
return. Privileged and User (Unprivileged) code can run in Thread mode.
• Handler mode is entered as a result of an exception. All code is privileged in
Handler mode.
2.1.2 Operating states
The processor can operate in one of two operating states:
• Thumb state. This is normal execution running 16-bit and 32-bit halfword aligned
Thumb instructions.
• Debug State. This is the state when in halting debug.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit