ARM Cortex-M3 User Manual

Introduction
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• Addition of a new input called IFLUSH. See Miscellaneous on page A-4.
• Addition of HMASTER ports. See DCode interface on page A-9 and System bus
interface on page A-10.
• Addition of the SWJ-DP. This is the standard CoreSight
™
debug port that
combines JTAG-DP and SW-DP. See About the DP on page 13-2.
• Addition of DWT_PCSR Register at address
0xE000101C . See DWT on
page 11-13.
• Addition of a new input called DNOTITRANS. See Unifying the code buses on
page 12-9.
• Errata fixes to the r0p0 release.
1.7.2 Differences in functionality between r1p0 and r1p1
In summary, the differences in functionality include:
• Data value matching for watchpoint generation has been made implementation
time configurable. See DWT on page 11-13.
• A define has been added to optionally implement architectural clock gating in the
ETM. For previous releases the architectural clock gate in the ETM was always
present.
• DAPCLKEN was required to be a static signal in r0p0 and r1p0. This
requirement has been removed for r1p1.
• SLEEPING signal now suppressed until current outstanding instruction fetch has
completed.
• Errata fixes to the r1p0 release.
1.7.3 Differences in functionality between r1p1 and r2p0
In summary, the differences in functionality include:
• Implementation time options have been added to select between different levels
of debug and trace support. This has replaced the previous TIEOFF_FPBEN and
TIEOFF_TRCENA options.
• New implementation option to enable the resetting of all registers within the
processor.
• Architectural clock gating inclusion is now controlled using one implementation
option.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit