ARM Cortex-M3 User Manual

Exceptions
5-28 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Table 5-10 lists the local faults.
Table 5-10 Faults
Fault Bit name Handler Notes Trap enable bit
Reset Reset cause Reset Any form of reset. RESETVCATCH
Vector Read error VECTTBL HardFault Bus error returned when reading
the vector table entry.
INTERR
uCode stack push error STKERR BusFault Failure when saving context using
hardware - bus error returned.
INTERR
uCode stack push error MSTKERR MemManage Failure when saving context using
hardware - MPU access violation.
INTERR
uCode stack pop error UNSTKERR BusFault Failure when restoring context
using hardware - bus error
returned.
INTERR
uCode stack pop error MUNSKERR MemManage Failure when restoring context
using hardware - MPU access
violation.
INTERR
Escalated to Hard Fault FORCED HardFault Fault occurred and handler is equal
or higher priority than current,
including fault within fault when
priority does not enable, or
Configurable fault disabled.
Includes SVC, BKPT and other
kinds of faults.
HARDERR
MPU mismatch DACCVIOL MemManage Violation or fault on MPU as a
result of data access.
MMERR
MPU mismatch IACCVIOL MemManage Violation or fault on MPU as a
result of instruction address.
MMERR
Pre-fetch error IBUSERR BusFault Bus error returned because of
instruction fetch. Faults only if
makes it to execute. Branch
shadow can fault and be ignored.
BUSERR
Precise data bus error PRECISERR BusFault Bus error returned because of data
access, and was precise, points to
instruction.
BUSERR

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit