ARM Cortex-M3 User Manual

System Debug
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-11
Unrestricted Access Non-Confidential
Table 11-4 describes the bit assignments of the Flash Patch Remap Register.
Flash Patch Comparator Registers
Use the Flash Patch Comparator Registers to store the values to compare with the PC
address.
The register address, access type, and Reset state are:
Access Read/write
Address
0xE0002008 , 0xE000200C , 0xE0002010 , 0xE0002014 , 0xE0002018 , 0xE000201C ,
0xE0002020 , 0xE0002024
Reset state Bit [0] (ENABLE) is reset to 1'b0.
Figure 11-4 shows the bit assignments of the Flash Patch Comparator Registers.
Figure 11-4 Flash Patch Comparator Registers bit assignments
Table 11-5 on page 11-12 describes the bit assignments of the Flash Patch Comparator
Registers.
Table 11-4 Flash Patch Remap Register bit assignments
Bits Field Function
[31:29] - Reserved. Read as b001. Hardwires the remap to the system space.
[28:5] REMAP Remap base address field.
[4:0] - Reserved. Read As Zero. Write Ignored.
31 0
COMP
12829 2
REPLACE
ENABLE
30
Reserved Reserved

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit