ARM Cortex-M3 User Manual

Embedded Trace Macrocell
14-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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14.3 ETM resources
Because the ETM does not generate data trace information, the lower bandwidth
reduces the requirement for complex triggering capabilities. This means that the ETM
does not include the following:
• internal comparators
• counters
• sequencers.
Table 14-7 lists the Cortex-M3 resources.
Table 14-7 Cortex-M3 resources
Feature Present on Cortex-M3 ETM
Architecture version ETMv3.4
Address comparator pairs 0
Data comparators 0
Context ID comparators 0
MMDs 0
Counters 0
Sequencer No
Start/stop block Yes
Embedded ICE comparators 4
External inputs 2
External outputs 0
Extended external inputs 0
Extended external input selectors 0
FIFOFULL Yes
FIFOFULL level setting Yes
Branch broadcasting Yes
ASIC Control Register No
Data suppression No

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit