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Embedded Trace Macrocell

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14.3.1 Periodic synchronization

The ETM uses a fixed synchronization packet generation frequency of every 1024 bytes

of trace.

14.3.2 Data and instruction address compare resources

The DWT provides four address comparators on the data bus that provide debug

functionality. Within the DWT unit, it is possible to specify the functions triggered by

a match, and one of these functions is to generate an ETM match input. These inputs are

presented to the ETM as Embedded In Circuit Emulator (ICE) comparator inputs.

A single DWT resource can trigger an ETM event and also generate instrumentation

trace directly from the same event.

Software access to registers Yes

Readable registers Yes

FIFO size 24 bytes

Minimum port size 8 bits

Maximum port size 8 bits

Normal port mode -

Normal half-rate clocking/1:1 Yes - asynchronous

Demux port mode -

Demux half-rate clocking/1:2 No

Mux port mode/2:1 No

1:4 port mode No

Dynamic port mode (including stalling) No. Supported by asynchronous port mode.

CPRT data No

Load PC first No

Fetch comparisons No

Load data traced No

Table 14-7 Cortex-M3 resources (continued)

Feature Present on Cortex-M3 ETM

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ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit