ARM Cortex-M3 User Manual

Embedded Trace Macrocell
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You can also individually configure the four DWT comparators to compare with the
execute PC to permit the ETM access to a PC compare resource. These inputs are
presented to the ETM as Embedded ICE comparator inputs.
Note
Using a DWT comparator as a PC comparator reduces the number of available data
address comparisons.
See DWT on page 11-13 for more information about the DWT unit.
External inputs
Two external inputs, ETMEXTIN[1:0], enable additional on-chip IP to generate
trigger/enable signals for the ETM.
Start/stop block
The start/stop block controls start/stop behavior by using the embedded ICE inputs to
the ETM. The DWT controls these inputs.
14.3.3 FIFO functionality
The FIFO size is 24 bytes.
A FIFOFULL output is provided to enable the core to be stalled when the FIFO reaches
a specific depth. Although stalling the core in a typical application is unlikely to be
acceptable, it provides a mechanism for enabling 100% trace that could be compared
with the partial trace obtained for a non-stalled run.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit