ARM Cortex-M3 User Manual

Nested Vectored Interrupt Controller
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-35
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Table 8-23 describes the bit assignments of the Bus Fault Status Register.
Usage Fault Status Register
The flags in the Usage Fault Status Register indicate the following errors:
• illegal combination of EPSR and instruction
• illegal PC load
• illegal processor state
• instruction decode error
• attempt to use a coprocessor instruction
• illegal unaligned access.
Table 8-23 Bus Fault Status Register bit assignments
Bits Field Function
[7] BFARVALID This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true
after a bus fault where the address is known. Other faults can clear this bit, such as a Mem
Manage fault occurring later.
If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler
must clear this bit. This prevents problems if returning to a stacked active Bus fault handler
whose BFAR value has been overwritten.
[6:5] - Reserved.
[4] STKERR Stacking from exception has caused one or more bus faults. The SP is still adjusted and the
values in the context area on the stack might be incorrect. The BFAR is not written.
[3] UNSTKERR Unstack from exception return has caused one or more bus faults. This is chained to the
handler, so that the original return stack is still present. SP is not adjusted from failing return
and new save is not performed. The BFAR is not written.
[2] IMPRECISERR Imprecise data bus error. It is a BusFault, but the Return PC is not related to the causing
instruction. This is not a synchronous fault. So, if detected when the priority of the current
activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a
lower priority activation. If a precise fault occurs before returning to a lower priority
exception, the handler detects both IMPRECISERR set and one of the precise fault status bits
set at the same time. The BFAR is not written.
[1] PRECISERR Precise data bus error return.
[0] IBUSERR Instruction bus error flag:
1 = instruction bus error
0 = no instruction bus error.
The IBUSERR flag is set by a prefetch error. The fault stops on the instruction, so if the error
occurs under a branch shadow, no fault occurs. The BFAR is not written.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit