ARM Cortex-M3 User Manual

System Debug
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-7
Unrestricted Access Non-Confidential
Note
You can configure any of the flash patch registers to be present or not present. Any
register that is configured as not present reads as zero.
Table 11-1 FPB register summary
Name Type Address Description
FP_CTRL Read/write
0xE0002000 See Flash Patch Control Register on page 11-8
FP_REMAP Read/write
0xE0002004 See Flash Patch Remap Register on page 11-9
FP_COMP0 Read/write
0xE0002008 See Flash Patch Comparator Registers on page 11-11
FP_COMP1 Read/write
0xE000200C See Flash Patch Comparator Registers on page 11-11
FP_COMP2 Read/write
0xE0002010 See Flash Patch Comparator Registers on page 11-11
FP_COMP3 Read/write
0xE0002014 See Flash Patch Comparator Registers on page 11-11
FP_COMP4 Read/write
0xE0002018 See Flash Patch Comparator Registers on page 11-11
FP_COMP5 Read/write
0xE000201C See Flash Patch Comparator Registers on page 11-11
FP_COMP6 Read/write
0xE0002020 See Flash Patch Comparator Registers on page 11-11
FP_COMP7 Read/write
0xE0002024 See Flash Patch Comparator Registers on page 11-11
PID4 Read-only
0xE0002FD0 Va lu e 0x04
PID5 Read-only 0xE0002FD4 Va lu e 0x00
PID6 Read-only 0xE0002FD8 Va lu e 0x00
PID7 Read-only 0xE0002FDC Va lu e 0x00
PID0 Read-only 0xE0002FE0 Va lu e 0x03
PID1 Read-only 0xE0002FE4 Va lu e 0xB0
PID2 Read-only 0xE0002FE8 Va lu e 0x2B
PID3 Read-only 0xE0002FEC Va lu e 0x00
CID0 Read-only 0xE0002FF0 Va lu e 0x0D

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit