ARM Cortex-M3 User Manual

System Debug
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-21
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Access Read-write
Reset state -
Figure 11-7 shows the bit assignments of the DTW Exception Overhead Count
Register.
Figure 11-7 DWT Exception Overhead Count Register bit assignments
Table 11-10 describes the bit assignments of the DWT Exception Overhead Count
Register.
DWT Sleep Count Register
Use the DWT Sleep Count Register to count the total number of cycles during which
the processor is sleeping.
The register address, access type, and Reset state are:
Address
0xE0001010
Access Read-write
Reset state
-
Figure 11-8 shows the bit assignments of the DTW Sleep Count Register.
Figure 11-8 DWT Sleep Count Register bit assignments
Reserved
31 8 7 0
SLEEPCNT
Table 11-10 DWT Exception Overhead Count Register bit assignments
Bits Field Function
[31:8] - Reserved.
[7:0] EXCCNT Current interrupt overhead counter value. Counts the total cycles spent in interrupt processing (for
example entry stacking, return unstacking, pre-emption). An event is emitted on counter overflow
(every 256 cycles). This counter initializes to 0 when enabled.
Clears to 0 on enabling.
Reserved
31 8 7 0
SLEEPCNT

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit