ARM Cortex-M3

Exceptions
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-35
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5.14.2 Pre-emption
Figure 5-7 shows what happens when an exception pre-empts the current ISR.
Figure 5-7 Pre-emption flowchart
5.14.3 Return
Figure 5-8 on page 5-36 shows how the processor restores the stacked ISR or tail-chains
to a late-arriving interrupt with higher priority than the stacked ISR.
Pre-empt
Read new PC from vector table
Push registers r0-r3, r12, LR,
PC, and xPSR onto SP stack
Late-arriving
interrupt?
Yes
No
Fill pipeline at PC
Late-arriving
interrupt?
Yes
No
Execute instructions
Synchronize
D busI bus