ARM Cortex-M3 User Manual

Power Management
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 7-9
Unrestricted Access Non-Confidential
Figure 7-5 PMU, WIC, and Cortex-M3 interconnect
The non-clocked circuitry can use the signals out of the WIC to deduce whether a
particular interrupt causes the WIC to generate a WAKEUP request, and to provide
alternative power reduction methods not supported by the WIC directly. All WIC
interrupt related pins are agnostic as to how many, or what combinations of INTISR,
NMI, or RXEV are attached as long as the same offset is used throughout the WIC.
The WIC can be disabled by using WICDISABLE, which is a signal indicating that
WIC-based SLEEPDEEP must not be entered, or if it has already been entered, that
WAKEUP be driven high and the SLEEPDEEP policy revert to non-WIC-based. A
debugger must hold this signal high when attached to the system to prevent power
isolation during debug.
The sources and causes of wake-up events are implementation defined and the
implementation can support any number of signals from two and greater. This enables
maximum flexibility over which set of NMI, debug request, interrupts, and RXEV are
used as potential wake-up sources.
CLAMPS
WAKEUP
WICENREQ
WICENACK
SLEEPDEEP
PMU
WAKEUP
WICSENSE
WICPEND
WICENACK WICDSREQn
WICDSACKn
WICENREQ WICMASK
WICCLEAR
WICLOAD
WIC
WICMASK
WICDSACKn
WICDSREQn
Cortex-M3
WICCLEAR
WICLOAD
INTISR/NMI/RXEV
SLEEPHOLDREQn
SLEEPDEEP
WICINT
0
INTERRUPTS
OR
SLEEPHOLDACKPMUn
SLEEPHOLDREQPMUn
SLEEPHOLDACKn
ISOLATEn
PWRDOWN
0
0
0
0
0
0
0
0
0
RETAINn

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit