ARM Cortex-M3 User Manual

Power Management
7-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Note
If the debug logic is included in a powered-down domain, then nTDOEN needs to be
handled carefully. It cannot be clamped to 0 because this enables it during power down.
Either:
• Insert inverters either side of the clamp.
• Ensure that the external system masks nTDOEN when the core is powered down.
•Clamp nTDOEN to 1 during power down.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit