ARM Cortex-M3 User Manual

Exceptions
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-9
Unrestricted Access Non-Confidential
5.4 Privilege and stacks
The processor supports two separate stacks:
Process stack
You can configure Thread mode to use the process stack. Thread mode
uses the main stack out of reset. SP_process is the Stack Pointer (SP)
register for the process stack.
Main stack
Handler mode uses the main stack. SP_main is the SP register for the
main stack.
Only one stack, the process stack or the main stack, is visible at any time. After pushing
the eight registers, the ISR uses the main stack, and all subsequent interrupt
pre-emptions use the main stack. The stack that saves context is as follows:
• Thread mode uses either the main stack or the process stack, depending on the
value of the CONTROL bit [1] that Move to Status Register (MSR) or Move to
Register from Status (MRS) can access. Appropriate EXC_RETURN values can
also set this bit when exiting an ISR. An exception that pre-empts a user thread
saves the context of the user thread on the stack that the Thread mode is using.
• All exceptions use the main stack for their own local variables.
Using the process stack for the Thread mode and the main stack for exceptions supports
Operating System (OS) scheduling. To reschedule, the kernel only requires to save the
eight registers not pushed by hardware, r4-r11, and to copy SP_process into the Thread
Control Block (TCB). If the processor saved the context on the main stack, the kernel
would have to copy the 16 registers to the TCB.
Note
MSR and MRS instructions have visibility of both stacks.
5.4.1 Stacks
The stack model is independent of privileged mode, that is, Thread mode can use the
process or main stack and be in user or privileged mode. All four combinations of stack
and privilege are possible. For a basic protected thread model, the user threads run in
Thread mode using the process stack, and the kernel and the interrupts run privileged
using the main stack.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit