ARM Cortex-M3 User Manual

Nested Vectored Interrupt Controller
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-41
Unrestricted Access Non-Confidential
Bus Fault Address Register
Use the Bus Fault Address Register to read the address of the location that generated a
Bus Fault.
The register address, access type, and Reset state are:
Address
E000ED38
Access Read/write
Reset state Unpredictable
Table 8-28 describes the bit assignments of the Bus Fault Address Register.
Auxiliary Fault Status Register
Use the Auxiliary Fault Status Register (AFSR) to determine additional system fault
information to software.
The AFSR flags map directly onto the AUXFAULT inputs of the processor, and a
single-cycle high level on an external pin causes the corresponding AFSR bit to become
latched as one. The bit can only be cleared by writing a one to the corresponding AFSR
bit.
When an AFSR bit is written or latched as one, an exception does not occur. If you
require an exception, you must use an interrupt.
The register address, access type, and Reset state are:
Address
0xE000ED3C
Access Read/write-clear
Reset state
0x00000000
Table 8-28 Bus Fault Address Register bit assignments
Bits Field Function
[31:0] ADDRESS Bus fault address field. ADDRESS is the data address of a faulted load or store attempt. When an
unaligned access faults, the address is the address requested by the instruction, even if that is not
the address that faulted. Flags in the Bus Fault Status Register indicate the cause of the fault. See
Bus Fault Status Register on page 8-34.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit