ARM Cortex-M3 User Manual

Bus Interface
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 12-3
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12.2 AMBA 3 compliance
The processor matches the AMBA 3 specification except for maintaining control
information during waited transfers. AMBA 3 AHB-Lite Protocol states that when the
slave is requesting wait states the master must not change the transfer type, except for
the following cases:
• IDLE transfer - the master is permitted to change the transfer type from IDLE to
NONSEQ.
• BUSY transfer, fixed length burst - the master is permitted to change the transfer
type from BUSY to SEQ.
• BUSY transfer, undefined length burst - the master is permitted to change from
BUSY to any other transfer type.
The processor does not match the given definition because it might change the access
type from SEQ or NONSEQ to IDLE during a waited transfer. In effect this cancels the
outstanding transfer that has not yet occurred because the previous access is wait-stated
and awaiting completion. This enables the processor to have a lower interrupt latency
and higher performance in wait-stated systems.
Note
Logic can be implemented external to Cortex-M3 if necessary to achieve total
compliance, but this is only required if peripherals require the control information to be
maintained through a waited transfer. One way of implementing this is to mask the
control information, such as HTRANS, while HREADY is low.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit