Signal Descriptions
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A.3 Miscellaneous
Table A-3 lists the leftover signals.
Table A-3 Miscellaneous signals
Name Direction Description
LOCKUP Output LOCKUP gives immediate indication of seriously errant kernel software.
This is the result of the core being locked up because of an unrecoverable
exception following the activation of the processor’s built in system state
protection hardware. For more information about the ARMv7-M
architectural lock up conditions see the ARMv7-M Architecture Reference
Manual.
CURRPRI[7:0] Output Indicates what priority interrupt (or base boost) is currently used.
CURRPRI represents the pre-emption priority, and does not indicate the
secondary priority.
HALTED Output In halting debug mode. HALTED remains asserted while the core is in
debug.
DBGRESTARTED Output Handshake for DBGRESTART.
TXEV Output Event transmitted as a result of SEV instruction. This is a single cycle pulse.
TRCENA Output Trace Enable. This signal reflects the setting of bit [24] of the Debug
Exception and Monitor Control Register. This signal gate the clock to the
TPIU and ETM blocks to reduce power consumption when trace is
disabled.
INTERNALSTATE[148:0] Output Internal state.
BIGEND Input Static endian select:
1 = big-endian
0 = little-endian
This signal is sampled at reset, and cannot be changed when reset is
inactive.
EDBGRQ Input External debug request.
PPBLOCK[5:0] Input Reserved. Must be tied to 6’b000000.
STCLK Input System Tick Clock.
STCALIB[25:0] Input System Tick Calibration.
RXEV Input Causes a wakeup from a WFE instruction.
VECTADDR[9:0] Input Reserved. Must be tied to 10'b0000000000.
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