ARM Cortex-M3 User Manual

Introduction
1-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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1.2 Components, hierarchy, and implementation
This section describes the components, hierarchy, and implementation of the processor.
It also describes the configurable options. The main blocks are:
• Processor core on page 1-5
• NVIC on page 1-7
• Bus matrix on page 1-7
• FPB on page 1-8
• DWT on page 1-8
• ITM on page 1-8
• MPU on page 1-9
• ETM on page 1-9
• AHB-AP on page 1-9
• AHB Trace Macrocell interface on page 1-9
• TPIU on page 1-9
• WIC on page 1-10
• SW/SWJ-DP on page 1-10
• Interrupts on page 1-11
• Observation on page 1-11
• ROM table on page 1-11.
Figure 1-1 on page 1-5 shows the structure of the processor.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit