Introduction
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1.2 Components, hierarchy, and implementation
This section describes the components, hierarchy, and implementation of the processor.
It also describes the configurable options. The main blocks are:
• Processor core on page 1-5
• NVIC on page 1-7
• Bus matrix on page 1-7
• FPB on page 1-8
• DWT on page 1-8
• ITM on page 1-8
• MPU on page 1-9
• ETM on page 1-9
• AHB-AP on page 1-9
• AHB Trace Macrocell interface on page 1-9
• TPIU on page 1-9
• WIC on page 1-10
• SW/SWJ-DP on page 1-10
• Interrupts on page 1-11
• Observation on page 1-11
• ROM table on page 1-11.
Figure 1-1 on page 1-5 shows the structure of the processor.