ARM Cortex-M3 User Manual

System Control
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Advanced High Performance Bus Access Port registers
Table 3-6 gives a summary of the Advanced High-performance Bus Access Port
(AHB-AP) registers. For a detailed description of the AHB-AP registers, see Chapter 11
System Debug.
3.1.4 Debug interface port registers
Table 3-7 gives a summary of the debug interface port registers. For a detailed
description of the debug interface port registers, see Chapter 13 Debug Port.
Table 3-6 AHB-AP register summary
Name Type Address
Reset
value
Control and Status Word Read/write
0x00 See Register
Transfer Address Read/write
0x04 -
Data Read/write Read/write
0x0C -
Banked Data 0 Read/write 0x10 -
Banked Data 1 Read/write
0x14 -
Banked Data 2 Read/write
0x18 -
Banked Data 3 Read/write
0x1C -
Debug ROM Address Read-only
0xF8 0xE000E000
Identification Register Read-only 0xFC 0x24770011
Table 3-7 Summary of Debug interface port registers
Name SWJ-DP SW-DP Description
ABORT Yes Yes The Abort Register
IDCODE Yes Yes The Identification Code Register
CTRL/STAT Yes Yes The Control/Status Register
SELECT Yes Yes The AP Select Register
RDBUFF Yes Yes The Read Buffer Register

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit