ARM Cortex-M3 User Manual

Bus Interface
12-6 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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12.4 DCode bus interface
The DCode interface is a 32-bit AHB-Lite bus. Data and debug accesses to Code
memory space (
0x00000000 - 0x1FFFFFFF ) are performed over this bus. Core data
accesses have a higher priority than debug accesses. This means that debug accesses are
waited until core accesses have completed when there are simultaneous core and debug
access to this bus.
Control logic in this interface converts unaligned data and debug accesses into two or
three (depending on the size and alignment of the unaligned access) aligned accesses.
This stalls any subsequent data or debug access until the unaligned access has
completed.
See Access alignment on page 12-11 for a description of unaligned accesses.
Note
It is strongly recommended that any external arbitration between the ICode and DCode
AHB bus interfaces ensures that DCode has a higher priority than ICode.
12.4.1 Exclusives
The DCode bus supports exclusive accesses. This is carried out using two sideband
signals, EXREQD and EXRESPD. For more information, see DCode interface on
page A-9.
For more information about semaphores and the local exclusive monitor see the ARM
Architecture Memory Model chapter in the ARMv7M ARM Architecture Reference
Manual.
12.4.2 Memory attributes
All DCode memory accesses are marked as cacheable and non-bufferable,
HPROTD[3:2] = 2'b10, and as allocate and non-shareable, MEMATTRD = 2'b01.
These attributes are hard wired. If an MPU is fitted, the MPU region attributes are
ignored for the DCode bus.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit