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Bus Interface

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HPROTI[0] indicates what is being fetched:

• 0 - instruction fetch

• 1 - vector fetch.

All ICode transactions are performed as non-sequentials.

12.3.1 Branch status signal

A branch status signal, BRCHSTAT, is exported on the Embedded Trace Macrocell

(ETM) interface that indicates if there are any branches in the pipeline. A prefetcher, for

example, can use this to prevent prefetching if a branch is about to be fetched. For more

information about the branch status signal, see Chapter 15 Embedded Trace Macrocell

Interface.

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ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit