ARM Cortex-M3 User Manual

Power Management
7-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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7.1 About power management
The processor extensively uses gated clocks to disable unused functionality, and
disables inputs to unused functional blocks, so that only actively used logic consumes
any dynamic power.
The ARMv7-M architecture supports system sleep modes that can stop the Cortex-M3
and system clocks for greater power reductions. These are described in System power
management on page 7-3.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit