ARM Cortex-M3 User Manual

Nested Vectored Interrupt Controller
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describes the field of the AFSR.
Software Trigger Interrupt Register
Use the Software Trigger Interrupt Register to pend an interrupt to trigger.
The register address, access type, and Reset state are:
Address
0xE000EF00
Access Write-only
Reset state
0x00000000
Figure 8-22 shows the bit assignments of the Software Trigger Interrupt Register.
Figure 8-22 Software Trigger Interrupt Register bit assignments
Table 8-30 describes the bit assignments of the Software Trigger Interrupt Register.
Table 8-29 Auxiliary Fault Status Register bit assignments
Bits Field Function
[31:0] IMPDEF Implementation defined. The bits map directly onto the signal assignment to the AUXFAULT inputs.
See Miscellaneous on page A-4.
931 0
Reserved INTID
8
Table 8-30 Software Trigger Interrupt Register bit assignments
Bits Field Function
[31:9] - Reserved.
[8:0] INTID Interrupt ID field. Writing a value to the INTID field is the same as manually pending an interrupt by
setting the corresponding interrupt bit in an Interrupt Set Pending Register.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit