ARM Cortex-M3 User Manual

Exceptions
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Table 5-11 shows debug faults.
5.12.3 Fault status registers and fault address registers
Each fault has a fault status register with a flag for that fault.
There are:
• three configurable fault status registers that correspond to the three configurable
fault handlers
• one hard fault status register
• one debug fault status register.
Depending on the cause, one of the five status registers has a bit set.
There are two Fault Address Registers (FAR):
• Bus Fault Address Register (BFAR)
• Memory Fault Address Register (MFAR).
A flag in the corresponding fault status register indicates when the address in the fault
address register is valid.
Note
BFAR and MFAR are the same physical register. Because of this, the BFARVALID and
MFARVALID bits are mutually exclusive.
Table 5-12 on page 5-31 shows the fault status registers and two fault address registers.
Table 5-11 Debug faults
Fault Flag Notes Trap enable bit
Internal halt request HALTED NVIC request from, for example, step, core halt -
Breakpoint BKPT SW breakpoint from patched instruction or FPB -
Watchpoint DWTTRAP Watchpoint match in DWT -
External EXTERNAL EDBGRQ line asserted -
Vector catch VCATCH Vector catch triggered. Corresponding FSR contains the
primary cause of the exception.
VC_xxx bit(s) or
RESETVCATCH set

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit