ARM Cortex-M3 User Manual

System Debug
11-40 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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AHB-AP Control and Status Word Register
Use this register to configure and control transfers through the AHB interface.
Figure 11-19 shows the bit assignments of the AHB-AP Control and Status Word
Register.
Table 11-28 AHB-AP register summary
Name Type Address Reset value Description
Control and Status Word Read/write
0x00 See Register See AHB-AP Control and Status Word Register
on page 11-40
Transfer Address Read/write
0x04 -See AHB-AP Transfer Address Register on
page 11-42
Data Read/write Read/write
0x0C - See AHB-AP Data Read/Write Register on
page 11-43
Banked Data 0 Read/write
0x10 -See AHB-AP Banked Data Registers 0-3 on
page 11-43
Banked Data 1 Read/write
0x14 -See AHB-AP Banked Data Registers 0-3 on
page 11-43
Banked Data 2 Read/write
0x18 -See AHB-AP Banked Data Registers 0-3 on
page 11-43
Banked Data 3 Read/write
0x1C -See AHB-AP Banked Data Registers 0-3 on
page 11-43
Debug ROM Address
Read only
0xF8 0xE00FF003 See AHB-AP Debug ROM Address Register on
page 11-43
Identification Register Read only
0xFC 0x24770011 See AHB-AP ID Register on page 11-44

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit