ARM Cortex-M3 User Manual

Power Management
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 7-5
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7.2.2 SLEEPDEEP
Figure 7-2 shows an example of how to reduce power consumption by stopping the
clock controller with SLEEPDEEP in the low-power state. When exiting low-power
state, the LOCK signal indicates that the PLL is stable, and it is safe to enable the
Cortex-M3 clock, ensuring that the processor is not re-started until the clocks are stable.
Figure 7-2 SLEEPDEEP power control example
To detect interrupts, the processor must receive the free-running FCLK in the
low-power state, unless the WIC is enabled. FCLK frequency can be reduced during
SLEEPDEEP assertion.
7.2.3 Extending sleep
You can use the SLEEPHOLDREQn and SLEEPHOLDACKn signals to extend the
sleep state. When the core is asleep with the SLEEPING signal raised,
SLEEPHOLDREQn can be asserted. In the following cycle, SLEEPHOLDACKn is
asserted to confirm the extension request. When a wake-up event occurs, SLEEPING is
de-asserted as normal but SLEEPHOLDACKn remains asserted and the core remains
sleeping. SLEEPHOLDREQn must be de-asserted to enable the core to wake up.
Halting the core also causes SLEEPHOLDACKn to be de-asserted and the sleep mode
to be exited as is the case with SLEEPING, irrespective of whether
SLEEPHOLDREQn is asserted or not.
If SLEEPHOLDREQn is asserted when SLEEPING is not high then the core does not
respond and only enters sleep mode when a sleep event occurs.
It is possible to assert SLEEPING for a very short time, for example if an interrupt is
asserted in parallel to the sleep event being executed. In this case, SLEEPHOLDREQn
might not be asserted in time for an acknowledge to occur and the sleep mode might not
be successfully extended. Your implementation must account for this case and ensure
that SLEEPHOLDREQn can be de-asserted if the sleep mode is exited without an
acknowledge.
Cortex M3 processor
SLEEPDEEP
HCLK
FCLK
EN
PLLCLKIN
Clock
controller
LOCK

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit