ARM Cortex-M3 User Manual

Embedded Trace Macrocell
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 14-23
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14.6.5 Cross trigger interface
Table 14-12 and Table 14-13 list the recommended Cross Trigger Interface (CTI)
connections for Cortex-M3 systems.
Table 14-11 Resource identification encoding
Resource type, bits [6:4] Index range, bits [3:0] Description of resource type
b010 0-3 DWT Comparator inputs (0-3)
b101 15 Trace Start/Stop resource
b110 0-1 ExtIn (0-1)
b110 15 HardWired (always True)
Table 14-12 Input connections
Trigger bit Source signal Source device Comments
[7] ETMTRIGOUT ETM Recommended if ETM is present.
[6] ETMTRIGGER[2] DWT Recommended.
[5] ETMTRIGGER[1] DWT Recommended.
[4] ETMTRIGGER[0] DWT Recommended.
[3] ACQCOMP ETB See Full.
[2] FULL ETB Recommended if an ETB is present. If a single ETB is shared
between multiple cores, only connect to the CTI of one of the
cores.
[1] User Defined - -
[0] DBGACK Core Compulsory.
Table 14-13 Trigger output connections
Trigger bit Source signal Source device Comments
[7] User defined - -
[6] User defined - -
[5] ETMEXTIN[1] ETM Compulsory if ETM is present.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit