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Embedded Trace Macrocell

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There is no connection from ETMDBGREQ of the ETM to the CTI. If required, this

signal must be ORed with an external debug request input, and trigger bit [0] from the

CTI.

[4] ETMEXTIN[0] ETM Compulsory if ETM is present.

[3] INTISR[y] NVIC See Full.

[2] INTISR[x] NVIC Compulsory. Any interrupt can be used.

[1] User defined - -

[0] EDBGRQ Core Compulsory.

Table 14-13 Trigger output connections (continued)

Trigger bit Source signal Source device Comments

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ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit