ARM Cortex-M3 User Manual

System Control
3-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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3.1 Summary of processor registers
This section describes the registers that control functionality. It contains the following:
• Nested Vectored Interrupt Controller registers
• Core debug registers on page 3-5
• System debug registers on page 3-6
• Debug interface port registers on page 3-10
• Memory Protection Unit registers on page 3-11
• Trace Port Interface Unit registers on page 3-12
• Embedded Trace Macrocell registers on page 3-13.
3.1.1 Nested Vectored Interrupt Controller registers
Table 3-1 gives a summary of the Nested Vectored Interrupt Controller (NVIC)
registers. For a detailed description of the NVIC registers, see Chapter 8 Nested
Vectored Interrupt Controller.
Table 3-1 NVIC registers
Name of register Type Address Reset value
Interrupt Control Type Register Read-only
0xE000E004
a
Auxiliary Control Register Read/write 0xE000E008 0x0
SysTick Control and Status Register Read/write 0xE000E010 0x00000000
SysTick Reload Value Register Read/write 0xE000E014 Unpredictable
SysTick Current Value Register Read/write clear
0xE000E018 Unpredictable
SysTick Calibration Value Register Read-only
0xE000E01C STCALIB
Irq 0 to 31 Set Enable Register Read/write
0xE000E100 0x00000000
....
....
....
Irq 224 to 239 Set Enable Register Read/write
0xE000E11C 0x00000000
Irq 0 to 31 Clear Enable Register Read/write 0xE000E180 0x00000000
....
....

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit