ARM Cortex-M3 User Manual

System Control
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 3-3
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Irq 224 to 239 Clear Enable Register Read/write
0xE000E19C 0x00000000
Irq 0 to 31 Set Pending Register Read/write 0xE000E200 0x00000000
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Irq 224 to 239 Set Pending Register Read/write
0xE000E21C 0x00000000
Irq 0 to 31 Clear Pending Register Read/write 0xE000E280 0x00000000
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Irq 224 to 239 Clear Pending Register Read/write
0xE000E29C 0x00000000
Irq 0 to 31 Active Bit Register Read-only 0xE000E300 0x00000000
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Irq 224 to 239 Active Bit Register Read-only
0xE000E31C 0x00000000
Irq 0 to 3 Priority Register Read/write 0xE000E400 0x00000000
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Irq 236 to 239 Priority Register Read/write
0xE000E4EC 0x00000000
CPUID Base Register Read-only 0xE000ED00 0x412FC230
Interrupt Control State Register Read/write or read-only 0xE000ED04 0x00000000
Vector Table Offset Register Read/write 0xE000ED08 0x00000000
Table 3-1 NVIC registers (continued)
Name of register Type Address Reset value

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit