ARM Cortex-M3 User Manual

Power Management
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 7-7
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in turn acknowledges the PMU. When all acknowledges are set, then the next
SLEEPDEEP mode is agreed to be a WIC mode sleep. Figure 7-3 shows an example of
this hand-shaking sequence.
Figure 7-3 WIC mode enable sequence
The next time the deep sleep mode is entered either by WFI, WFE, or sleep-on-exit then
the processor loads the WIC with a suitable mask using WICLOAD and WICMASK to
enable the required interrupts and events, or both, to cause a wake-up. A logic-1 in the
WICSENSE and WICMASK vector, or both, indicates that the WIC must wake up in
response to the corresponding WICINT signal. The mask vector is held by the WIC
when programmed. WICPEND is a vector of pending interrupts captured by the WIC
block. This provides a latched indication of the occurrence of any enabled and detected
interrupts which occurred while the NVIC was sleeping. This enables pulse-interrupts
to be used in combination with WIC based sleep methods.
The PMU must assert SLEEPHOLDREQn to prevent the processor from waking up
during a power-down sequence. When it has been acknowledged by
SLEEPHOLDACKn then the PMU can proceed to power down the system. When the
WIC detects a wake-up trigger from an interrupt or an event then it signals to the PMU
to power up the processor using the WA K E U P pin. When the power is restored, the
processor processes the event or interrupts or both given by the WICPEND signal that
has stored the interrupts that have occurred including ones that do not cause a wake-up
event because their priorities are not sufficient. When awake, the processor asserts
WICLEAR to clear the mask contents stored in the WIC. The processor then proceeds
with executing instructions until another WIC mode sleep event occurs.
Figure 7-4 on page 7-8 shows an example of the previously described functionality. It
also shows the driving of ISOLATEn, RETAINn and PWRDOWN for use with state
retention cells.
FCLK
WICENREQ
WICENACK
WICDSREQn
WICDSACKn

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit